Invention Grant
- Patent Title: Frequency dividing circuit, frequency dividing method and phase locked loop
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Application No.: US17708944Application Date: 2022-03-30
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Publication No.: US11595051B2Publication Date: 2023-02-28
- Inventor: Tengxiao Jiang , Zhiyu Zhuang , Yiren Huang
- Applicant: MAXIO Technology (Hangzhou) Co., Ltd.
- Applicant Address: CN Hangzhou
- Assignee: MAXIO Technology (Hangzhou) Co., Ltd.
- Current Assignee: MAXIO Technology (Hangzhou) Co., Ltd.
- Current Assignee Address: CN Hangzhou
- Agency: Westman, Champlin & Koehler, P.A.
- Priority: CN202110340731.0 20210330
- Main IPC: H03L7/197
- IPC: H03L7/197 ; H03L7/081 ; H03L7/089 ; H03L7/093

Abstract:
Disclosed is a frequency dividing circuit, a frequency dividing method and a phase locked loop. The frequency dividing circuit comprises: a clock selection unit outputting a first clock signal, select a second clock signal lagging behind the first clock signal by (½-1/M) of one phase; an integer frequency dividing unit performing frequency division on the first clock signal to provide a frequency-divided clock signal; a trigger unit triggering the frequency-divided clock signal according to the second clock signal to obtain a modulation clock signal; a switching signal unit providing a switching signal according to the modulation clock signal and a preset target output frequency. The clock selection unit selects and further outputs a third clock signal as the first clock signal according to the target phase selection information, to adjust the frequency of the frequency-divided clock signal, reduce noise and improve loop bandwidth of the phase locked loop.
Public/Granted literature
- US20220321134A1 FREQUENCY DIVIDING CIRCUIT, FREQUENCY DIVIDING METHOD AND PHASE LOCKED LOOP Public/Granted day:2022-10-06
Information query
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