Invention Grant
- Patent Title: Low resistivity wafer and method of manufacturing thereof
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Application No.: US16915095Application Date: 2020-06-29
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Publication No.: US11598023B2Publication Date: 2023-03-07
- Inventor: Yasuhito Narushima , Masayuki Uto
- Applicant: SUMCO CORPORATION
- Applicant Address: JP Tokyo
- Assignee: SUMCO CORPORATION
- Current Assignee: SUMCO CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: Greenblum & Bernstein, P.L.C.
- Main IPC: H01L29/167
- IPC: H01L29/167 ; C30B29/06 ; C30B15/30 ; C30B15/04

Abstract:
A semiconductor wafer including a single crystal doped with a dopant, wherein a resistivity of the wafer is 0.7 mΩ-cm or less, and wherein a striation height of the wafer is 6 mm or more. The resistivity of the wafer may be 0.8 mΩ-cm or less, and the striation height may be 13 mm or more. The resistivity of the wafer may be 0.7 mΩ-cm or less, and the striation may be 22 mm or more. Example features relate to a method of making a semiconductor wafer that includes adding a dopant to a silicon melt, rotationally pulling a crystal from the silicon melt, and applying a magnetic field of 3000 G or more such that the semiconductor wafer has a resistivity that is equal to or less than 0.8 mΩ-cm and a striation height that is equal to or more than 13 mm.
Public/Granted literature
- US20210404087A1 LOW RESISTIVITY WAFER AND METHOD OF MANUFACTURING THEREOF Public/Granted day:2021-12-30
Information query
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