Invention Grant
- Patent Title: Test apparatus and test method to a memory device
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Application No.: US17155043Application Date: 2021-01-21
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Publication No.: US11598806B2Publication Date: 2023-03-07
- Inventor: Yu-Wei Tseng , Chih-Ming Chang , Wan-Chun Fang , Jui-Chung Hsu , Chun-Hsi Li
- Applicant: NANYA TECHNOLOGY CORPORATION
- Applicant Address: TW New Taipei
- Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee Address: TW New Taipei
- Agency: CKC & Partners Co., LLC
- Main IPC: G01R31/317
- IPC: G01R31/317

Abstract:
A test system is disclosed. The test system includes a tester, a first voltage stabilization circuit, and a device under test (DUT). The tester generates a first operational voltage and a control signal. The first voltage stabilization circuit transmits a second operational voltage, associated with the first operational voltage, to a socket board. The DUT operates with the second operational voltage received through the socket board. The first voltage stabilization circuit is further configured to control, according to the control signal, the second operational voltage to have a first voltage level when the DUT is operating.
Public/Granted literature
- US20220229109A1 TEST APPARATUS AND TEST METHOD TO A MEMORY DEVICE Public/Granted day:2022-07-21
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