An error correction system is disclosed. The error correction system is applied to a storage system. The error correction system generates X first operation codes, Y second operation codes and a third operation code based on the storage system. The error correction system includes an error state determining circuit and M decoding circuits. The error state determining circuit is configured to identify a current error state. When a plurality of pieces of data have a 1-bit error, the M decoding circuits are configured to execute decoding processing on the X first operation codes and the Y second operation codes, to obtain whether there is erroneous data in the bytes corresponding to the decoding circuits and locate a bit to which the erroneous data belongs.