An electronic device includes a memory controller having an improved operation speed. The memory controller includes a main memory, a processor configured to generate commands for accessing data stored in the main memory, a scheduler configured to store the commands and output the commands according to a preset criterion, a cache memory configured to cache and store data accessed by the processor among the data stored in the main memory, and a hazard filter configured to store information on an address of the main memory corresponding to a write command among the commands, provide a pre-completion response for the write command to the scheduler upon receiving the write command, and provide the write command to the main memory.