Invention Grant
- Patent Title: Inter-die memory-bus transaction in a seamlessly integrated microcontroller chip
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Application No.: US17315270Application Date: 2021-05-08
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Publication No.: US11599489B2Publication Date: 2023-03-07
- Inventor: Scott David Kee
- Applicant: AyDeeKay LLC
- Applicant Address: US CA Aliso Viejo
- Assignee: AyDeeKay LLC
- Current Assignee: AyDeeKay LLC
- Current Assignee Address: US CA Aliso Viejo
- Agent Steven Stupp
- Main IPC: G06F3/00
- IPC: G06F3/00 ; G06F13/26 ; G06F13/40 ; G06F3/06 ; G06F12/06 ; G06F12/0866 ; G06F13/16 ; G06F13/28 ; G06F13/364 ; G06F13/42 ; G06F13/14 ; G06F21/76

Abstract:
Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.
Public/Granted literature
- US20210326277A1 Inter-Die Memory-Bus Transaction in a Seamlessly Integrated Microcontroller Chip Public/Granted day:2021-10-21
Information query