A memory device includes: a plurality of memory cells grouped into a plurality of planes; page buffer groups corresponding to respective ones of the plurality of planes, the page buffer groups including a plurality of page buffer circuits, each of the plurality of page buffer circuits including cache latches which are configured to receive data to be stored in memory cells in the plurality of planes; and control logic for controlling the page buffer groups to simultaneously initialize cache latches corresponding to at least two planes, among the cache latches, in response to a multi-plane program command, wherein the multi-plane program command instructs a multi-plane program operation of simultaneously storing data in plural planes among the plurality of planes.