Invention Grant
- Patent Title: Multilayer ceramic capacitor
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Application No.: US17118667Application Date: 2020-12-11
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Publication No.: US11600440B2Publication Date: 2023-03-07
- Inventor: Suguru Nakano , Satoshi Muramatsu , Risa Hojo , Yoshiyuki Nomura
- Applicant: Murata Manufacturing Co., Ltd.
- Applicant Address: JP Nagaokakyo
- Assignee: Murata Manufacturing Co., Ltd.
- Current Assignee: Murata Manufacturing Co., Ltd.
- Current Assignee Address: JP Nagaokakyo
- Agency: Keating & Bennett, LLP
- Priority: JPJP2019-224654 20191212
- Main IPC: H01G4/12
- IPC: H01G4/12 ; H01G4/30 ; H01G4/008 ; H01G4/012

Abstract:
A multilayer ceramic capacitor includes: a laminate including dielectric layers and internal electrode layers; and external electrodes on the main surfaces of the laminate. The laminate further includes a first via conductor, a second via conductor, a third via conductor, and a fourth via conductor that connect the internal electrode layers and the external electrodes. The external electrodes include first external electrodes, second external electrodes, third external electrodes, and fourth external electrodes, each connected to the respective end surfaces of the via conductor. Each of the external electrodes does not extend to the side surfaces of the laminate. A ratio W/L of a dimension W in the width direction of the multilayer ceramic capacitor to a dimension L in the length direction of the multilayer ceramic capacitor is about 0.85 or more and about 1 or less. The dimension L in the length direction of the multilayer ceramic capacitor is about 750 μm or smaller.
Public/Granted literature
- US20210183570A1 MULTILAYER CERAMIC CAPACITOR Public/Granted day:2021-06-17
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