Invention Grant
- Patent Title: Through-silicon via with low-K dielectric liner
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Application No.: US16921561Application Date: 2020-07-06
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Publication No.: US11600551B2Publication Date: 2023-03-07
- Inventor: Ming-Fa Chen
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L23/48 ; H01L21/3065 ; H01L21/3105 ; H01L21/311 ; H01L23/00 ; H01L21/683
Abstract:
A semiconductor substrate having a through-silicon via with an air gap interposed between the through-silicon via and the semiconductor substrate is provided. An opening is formed partially through the semiconductor substrate. The opening is first lined with a first liner and then the opening is filled with a conductive material. A backside of the semiconductor substrate is thinned to expose the first liner, which is subsequently removed and a second liner formed with a low-k or extra low-k dielectric is formed in its place.
Public/Granted literature
- US20200335428A1 Through-Silicon Via With Low-K Dielectric Liner Public/Granted day:2020-10-22
Information query
IPC分类:
