Invention Grant
- Patent Title: Interconnection structures to improve signal integrity within stacked dies
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Application No.: US17391290Application Date: 2021-08-02
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Publication No.: US11600554B2Publication Date: 2023-03-07
- Inventor: Walker J. Turner , Yaping Zhou , John M. Wilson
- Applicant: Nvidia Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Nvidia Corporation
- Current Assignee: Nvidia Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: H01L23/528
- IPC: H01L23/528 ; H01L23/48 ; H01L25/065 ; H01L25/00 ; H01L23/00

Abstract:
A device including a stack of dies. Each of the dies can have unit stair-step conductive paths of connection features which include through-die via structures and routing structures. The unit stair-step conductive paths of one of the dies can be interconnected to another one of the unit stair-step conductive paths of another one of the dies to form one of a plurality conductive stair-case structures through two or more of the dies. The unit stair-step conductive paths can be connected to reduce signal cross talk between the conductive stair-case structures whereby at least some of the conductive stair-case structures are connected to transmit a same polarity of electrical signals are spatially separated in a dimension that is perpendicular to a major surface of the dies. A method of manufacturing the device is also disclosed.
Public/Granted literature
- US20230034619A1 INTERCONNECTION STRUCTURES TO IMPROVE SIGNAL INTEGRITY WITHIN STACKED DIES Public/Granted day:2023-02-02
Information query
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