Invention Grant
- Patent Title: Layouts for conductive layers in integrated circuits
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Application No.: US17351711Application Date: 2021-06-18
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Publication No.: US11600568B2Publication Date: 2023-03-07
- Inventor: Wan-Yu Lo , Chung-Hsing Wang , Chin-Shen Lin , Kuo-Nan Yang , Meng-Xiang Lee , Hao-Tien Kan , Jhih-Hong Ye
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Merchant & Gould P.C.
- Main IPC: H01L23/528
- IPC: H01L23/528 ; H01L23/522

Abstract:
Various layouts for conductive interconnects in the conductor layers in an integrated circuit are disclosed. Some or all of the conductive interconnects are included in a power delivery system. In general, the conductive interconnects in a first conductor layer are arranged according to an orthogonal layout and the conductive interconnects in a second conductor layer are arranged according to a non-orthogonal layout. Conductive stripes in a transition conductor layer positioned between the first and the second conductor layers electrically connect the conductive interconnects in the first conductor layer to the conductive interconnects in the second conductor layer.
Public/Granted literature
- US20220406716A1 LAYOUTS FOR CONDUCTIVE LAYERS IN INTEGRATED CIRCUITS Public/Granted day:2022-12-22
Information query
IPC分类: