Invention Grant
- Patent Title: Methods and apparatus for via last through-vias
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Application No.: US16378643Application Date: 2019-04-09
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Publication No.: US11600653B2Publication Date: 2023-03-07
- Inventor: Szu-Ying Chen , Pao-Tung Chen , Dun-Nian Yaung , Jen-Cheng Liu
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L27/146
- IPC: H01L27/146 ; H01L23/498 ; H01L21/768 ; H01L23/538

Abstract:
Methods for forming via last through-vias. A method includes providing an active device wafer having a front side including conductive interconnect material disposed in dielectric layers and having an opposing back side; providing a carrier wafer having through vias filled with an oxide extending from a first surface of the carrier wafer to a second surface of the carrier wafer; bonding the front side of the active device wafer to the second surface of the carrier wafer; etching the oxide in the through vias in the carrier wafer to form through oxide vias; and depositing conductor material into the through oxide vias to form conductors that extend to the active carrier wafer and make electrical contact to the conductive interconnect material. An apparatus includes a carrier wafer with through oxide vias extending through the carrier wafer to an active device wafer bonded to the carrier wafer.
Public/Granted literature
- US20190237505A1 Methods and Apparatus for Via Last Through-Vias Public/Granted day:2019-08-01
Information query
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