Invention Grant
- Patent Title: Connection terminal pattern and layout for three-level buck regulator
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Application No.: US16444844Application Date: 2019-06-18
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Publication No.: US11601051B2Publication Date: 2023-03-07
- Inventor: Chengyue Yu , Zhen Ning Low , Guoyong Guo , Jiwei Chen
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Patterson & Sheridan, LLP
- Main IPC: H02M3/156
- IPC: H02M3/156 ; G06F1/3287 ; H01L23/50 ; H01L23/00 ; H02M3/07 ; H02M3/158 ; H02M7/483 ; H02M1/00

Abstract:
Certain aspects of the present disclosure generally relate to a connection terminal pattern and layout for a three-level buck regulator. One example electronic module generally includes a substrate, an integrated circuit (IC) package disposed on the substrate and comprising transistors of a three-level buck regulator, a capacitive element of the three-level buck regulator disposed on the substrate, and an inductive element of the three-level buck regulator disposed on the substrate. In certain aspects, the capacitive element and the inductive element may be disposed adjacent to different sides of the IC package.
Information query
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