Invention Grant
- Patent Title: System and method for generating sub harmonic locked frequency division and phase interpolation
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Application No.: US17307489Application Date: 2021-05-04
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Publication No.: US11601116B2Publication Date: 2023-03-07
- Inventor: Gunjan Mandal , Vishnu Kalyanamahadevi Gopalan Jawarlal
- Applicant: SAMSUNG ELECTRONICS CO., LTD.
- Applicant Address: KR Suwon-si
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR Suwon-si
- Agency: F. Chau & Associates, LLC
- Priority: IN202141004388 20210202
- Main IPC: H03K3/03
- IPC: H03K3/03 ; H03K5/01 ; H03K5/00

Abstract:
A system for generating a sub-harmonically injection locked phase interpolated output signal. The system comprises ring oscillator (RO) circuitry to generate an output oscillator signal in response to a periodic input signal. The RO circuitry includes a plurality of differential delay RO stages interconnected in cascade within a closed loop, where each RO stage is configured to establish a corresponding delayed version of the output oscillator signal successively shifted in phase by a predetermined phase difference based on a predetermined interpolation mapping scheme. The system further comprises signal injection circuitry coupled to the RO circuitry to apply a first signal having a first input phase and a second signal having a second input phase to the plurality of differential delay RO stages based on the predetermined interpolation mapping scheme to lock a frequency of the output oscillator signal at one half the frequency of the periodic input signal.
Public/Granted literature
- US20220247392A1 SYSTEM AND METHOD FOR GENERATING SUBHARMONIC LOCKED FREQUENCY DIVISION AND PHASE INTERPOLATION Public/Granted day:2022-08-04
Information query
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