Invention Grant
- Patent Title: Initialization circuit of delay locked loop
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Application No.: US17304628Application Date: 2021-06-23
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Publication No.: US11601130B2Publication Date: 2023-03-07
- Inventor: Gaurav Agrawal , Deependra Kumar Jain , Krishna Thakur
- Applicant: NXP B.V.
- Applicant Address: NL Eindhoven
- Assignee: NXP B.V.
- Current Assignee: NXP B.V.
- Current Assignee Address: NL Eindhoven
- Main IPC: H03L7/10
- IPC: H03L7/10 ; H03L7/081 ; H03L7/089

Abstract:
An initialization circuit of a delay locked loop (DLL) includes a sense circuit and a control circuit. The sense circuit receives an enable signal, a reference clock signal, and various delayed reference clock signals, and outputs another enable signal. The control circuit receives the two enable signals and outputs and provides a control signal to a loop filter of the DLL to control a delay value associated with the DLL. The control signal is provided to the loop filter such that the delay value associated with the DLL equals a predetermined delay value for a predetermined time duration. Further, after a lapse of the predetermined time duration, the delay value associated with the DLL increases until a difference between a time period of the reference clock signal and the delay value equals a threshold value.
Public/Granted literature
- US20220416796A1 INITIALIZATION CIRCUIT OF DELAY LOCKED LOOP Public/Granted day:2022-12-29
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