Invention Grant
- Patent Title: Trim value loading management in a memory sub-system
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Application No.: US17068327Application Date: 2020-10-12
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Publication No.: US11604601B2Publication Date: 2023-03-14
- Inventor: Steven Michael Kientz , Vamsi Pavan Rayaprolu
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Lowenstein Sandler LLP
- Main IPC: G06F3/06
- IPC: G06F3/06

Abstract:
A memory sub-system to, in response to a power up, initiate a first loading process associated with a set of trim values, wherein the first loading process includes loading a sequence of the set of trim values to one or more registers of the memory sub-system. An operation associated with a memory unit of the memory sub-system is identified. A portion of the set of trim values corresponding to the operation associated with the memory unit is identified. The memory sub-system executes a second loading process comprising loading the portion of the set of trim values corresponding to the operation associated with the memory unit. The operation is executed using the portion of the set of trim values loaded into the one or more registers associated with the memory unit.
Public/Granted literature
- US20220113890A1 TRIM VALUE LOADING MANAGEMENT IN A MEMORY SUB-SYSTEM Public/Granted day:2022-04-14
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