A display apparatus includes: a display panel including a display region, a first peripheral region, and a second peripheral region; and a circuit substrate. The display panel includes a gate drive circuit, n number of clock main lines, an outer main line and an inner main line, and a plurality of branch wiring lines. The first peripheral region includes a plurality of unit regions. The plurality of unit regions includes a first unit region and a second unit region. A resistance value of the at least one branch wiring line between the inner main line and the outer main line in the first unit region is smaller than a resistance value of the at least one branch wiring line between the inner main line and the outer main line in the second unit region.