Invention Grant
- Patent Title: Integrated circuits with doped gate dielectrics
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Application No.: US17181970Application Date: 2021-02-22
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Publication No.: US11605537B2Publication Date: 2023-03-14
- Inventor: Chung-Liang Cheng , Yen-Yu Chen
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L21/32 ; H01L29/51 ; H01L21/02 ; H01L21/28 ; H01L29/66 ; H01L29/49
Abstract:
Examples of an integrated circuit with a gate structure and a method for forming the integrated circuit are provided herein. In some examples, a workpiece is received that includes a substrate having a channel region. A gate dielectric is formed on the channel region, and a layer containing a dopant is formed on the gate dielectric. The workpiece is annealed to transfer the dopant to the gate dielectric, and the layer is removed after the annealing. In some such examples, after the layer is removed, a work function layer is formed on the gate dielectric and a fill material is formed on the work function layer to form a gate structure.
Public/Granted literature
- US20210175076A1 Integrated Circuits with Doped Gate Dielectrics Public/Granted day:2021-06-10
Information query
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