Invention Grant
- Patent Title: Chip package assembly and method for manufacturing the same
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Application No.: US17175018Application Date: 2021-02-12
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Publication No.: US11605578B2Publication Date: 2023-03-14
- Inventor: Shijie Chen
- Applicant: SILERGY SEMICONDUCTOR TECHNOLOGY (HANGZHOU) LTD
- Applicant Address: CN Hangzhou
- Assignee: SILERGY SEMICONDUCTOR TECHNOLOGY (HANGZHOU) LTD
- Current Assignee: SILERGY SEMICONDUCTOR TECHNOLOGY (HANGZHOU) LTD
- Current Assignee Address: CN Hangzhou
- Agency: Harness, Dickey & Pierce, P.L.C.
- Priority: CN201810069713.1 20180124
- Main IPC: H01L23/495
- IPC: H01L23/495 ; H01L21/48 ; H01L23/31

Abstract:
A chip package assembly and a method for manufacturing the same are provided. A die is attached to one of pins located around a chip carrier, so that an electronic component such as a diode is packaged in the chip package assembly and is electrically connected in series with other dies inside the package, thereby improving the degree of integration of the chip package assembly, and reducing a volume of the external circuit.
Public/Granted literature
- US20210166999A1 Chip Package Assembly And Method For Manufacturing The Same Public/Granted day:2021-06-03
Information query
IPC分类: