Invention Grant
- Patent Title: Three-dimensional (3D) integrated circuit with passive elements formed by hybrid bonding
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Application No.: US16906509Application Date: 2020-06-19
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Publication No.: US11605620B2Publication Date: 2023-03-14
- Inventor: Je-Hsiung Lan , Ranadeep Dutta , Jonghae Kim
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Patterson + Sheridan, L.L.P.
- Main IPC: H01L25/16
- IPC: H01L25/16 ; H01L23/00 ; H01L49/02 ; H01L27/092 ; H03H9/17

Abstract:
A three-dimensional integrated circuit (3DIC) and techniques for fabricating a 3DIC. An example semiconductor device generally includes an integrated circuit (IC) having a first plurality of pads coupled to components of the IC, wherein a first oxide material is disposed between the first plurality of pads, and a second plurality of pads, wherein at least a portion of the first plurality of pads is bonded to at least a portion of the second plurality of pads, and wherein a second oxide material is disposed between the second plurality of pads and is bonded to the first oxide material b. The semiconductor device may also include a substrate disposed above the second plurality of pads, one or more passive devices adjacent to the substrate, and one or more vias formed through the substrate, wherein at least one of the second plurality of pads is coupled to the one or more vias.
Public/Granted literature
- US20210398957A1 THREE-DIMENSIONAL (3D) INTEGRATED CIRCUIT WITH PASSIVE ELEMENTS FORMED BY HYBRID BONDING Public/Granted day:2021-12-23
Information query
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