Negative transconductance device and multi-valued inverter logic device using the same
Abstract:
A negative transconductance device is disclosed. The negative transconductance device includes a first transistor having a P-type semiconductor channel, a second transistor having an N-type semiconductor channel, and a third transistor having an ambipolar semiconductor channel and positioned between the first and second transistors. A first drain electrode of the first transistor is electrically connected to a third source electrode of the third transistor, and a drain electrode of the third transistor is electrically connected to a second source electrode of the second transistor.
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