Invention Grant
- Patent Title: Immunity evaluation system and immunity evaluation method
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Application No.: US17455580Application Date: 2021-11-18
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Publication No.: US11609267B2Publication Date: 2023-03-21
- Inventor: Isao Houda , Aya Ohmae , Umberto Paoletti
- Applicant: Hitachi, Ltd.
- Applicant Address: JP Tokyo
- Assignee: Hitachi, Ltd.
- Current Assignee: Hitachi, Ltd.
- Current Assignee Address: JP Tokyo
- Agency: Crowell & Moring LLP
- Priority: JPJP2021-025746 20210219
- Main IPC: G01R31/309
- IPC: G01R31/309 ; H05K1/02 ; G01R1/067

Abstract:
Provided is an immunity evaluation system that enables design feedback in consideration of a subject wiring and an improvement amount for improving an electromagnetic noise resistance of a circuit board. An immunity evaluation device includes: a storage unit configured to store characteristic data including probe-circuit board wiring coupling characteristics which are determined by a combination of a near-field probe and circuit board characteristics, and a test result; and an IC reaching signal level estimation unit configured to estimate a signal level reaching a terminal of an evaluation target IC. The immunity evaluation device receives board design information, information of the near-field probe, and test waveform instruction information of a signal applied to the near-field probe. The IC reaching signal level estimation unit reads the coupling characteristics from the storage unit based on the board design information of a test subject circuit board and the information of the near-field probe, and outputs a value of the IC reaching signal level reaching a terminal of the evaluation target IC from the board design information of the test subject circuit board, the information of the near-field probe, and the coupling characteristics.
Public/Granted literature
- US20220268836A1 Immunity Evaluation System and Immunity Evaluation Method Public/Granted day:2022-08-25
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