- Patent Title: Wireline transceiver with internal and external clock generation
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Application No.: US17643995Application Date: 2021-12-13
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Publication No.: US11609597B2Publication Date: 2023-03-21
- Inventor: Li Cai , Sau Siong Chong , Chang-Feng Loi , Lawrence Tse
- Applicant: Marvell Asia Pte Ltd
- Applicant Address: SG Singapore
- Assignee: Marvell Asia Pte Ltd
- Current Assignee: Marvell Asia Pte Ltd
- Current Assignee Address: SG Singapore
- Main IPC: G06F1/08
- IPC: G06F1/08

Abstract:
An integrated circuit device, having functional circuitry driven by a clock signal, includes a first clock path for accepting an external clock signal where the first clock path includes first biasing circuitry configured to controllably pass the external clock signal, a second clock path for accepting an external frequency reference signal where the second clock path includes internal clock generation circuitry configured to generate an internal clock signal from the external frequency reference signal and second biasing circuitry configured to controllably pass the external frequency reference signal to the internal clock generation circuitry, and selector circuitry configured to select, based on user input, a clock output to drive the functional circuitry of the integrated circuit device. The clock output is selected from between (i) an output of the first clock path, and (ii) an output of the second clock path.
Public/Granted literature
- US20230055107A1 WIRELINE TRANSCEIVER WITH INTERNAL AND EXTERNAL CLOCK GENERATION Public/Granted day:2023-02-23
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