A data processing system comprising: a memory system comprising a plurality of memory devices, each of which comprises a first error correction unit and a plurality of cell array regions each having a plurality of memory cells coupled in an array to a plurality of word lines and a plurality of bit lines; and a host comprising a second error correction unit for correcting an error of data transferred from the memory system, and suitable for generating error correction information on the error correction operation of the second error correction unit, setting error correcting strengths to the respective memory devices using the error correction information and log information, and performing counter-error operations on the respective memory devices according to the error correcting strengths.