Invention Grant
- Patent Title: High speed SRAM using enhance wordline/global buffer drive
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Application No.: US17375149Application Date: 2021-07-14
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Publication No.: US11610612B2Publication Date: 2023-03-21
- Inventor: Ashish Kumar , Dipti Arya
- Applicant: STMicroelectronics International N.V.
- Applicant Address: CH Geneva
- Assignee: STMicroelectronics International N.V.
- Current Assignee: STMicroelectronics International N.V.
- Current Assignee Address: CH Geneva
- Agency: Crowe & Dunlevy
- Main IPC: G11C7/10
- IPC: G11C7/10 ; G11C7/22 ; G11C5/14 ; G11C8/08

Abstract:
A row decoder includes decoder logic generating an initial word line signal, and two inverters. The first inverter is formed by a first p-channel transistor having a source coupled to a supply voltage and a gate receiving the initial word line signal. The second inverter is formed by a first n-channel transistor having a drain coupled to a drain of the first p-channel transistor, a source coupled to a shared ground line, and a gate receiving the initial word line signal. An inverse word line signal is generated at the drain of the first n-channel transistor. A second inverter inverts the inverse word line signal to produce a word line signal. Negative bias generation circuitry generates a negative bias voltage on the shared ground line when the initial word line signal is logic high, and otherwise couples the shared ground line to ground.
Public/Granted literature
- US20220020405A1 HIGH SPEED SRAM USING ENHANCE WORDLINE/GLOBAL BUFFER DRIVE Public/Granted day:2022-01-20
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