Invention Grant
- Patent Title: Technique for reducing gate induced drain leakage in DRAM cells
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Application No.: US17314275Application Date: 2021-05-07
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Publication No.: US11610972B2Publication Date: 2023-03-21
- Inventor: Sipeng Gu , Qintao Zhang
- Applicant: Applied Materials, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Applied Materials, Inc.
- Current Assignee: Applied Materials, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: KDB Firm PLLC
- Main IPC: H01L29/40
- IPC: H01L29/40 ; H01L29/423 ; H01L21/02 ; H01L21/265

Abstract:
A method of forming a metal oxide semiconductor field effect transistor with improved gate-induced drain leakage performance, the method including providing a semiconductor substrate having a gate trench formed therein, performing an ion implantation process on upper portions of sidewalls of the gate trench to make the upper portions more susceptible to oxidation relative to non-implanted lower portions of the sidewalls, and performing an oxidation process on surfaces of the substrate, wherein the implanted upper portions of the sidewalls develop a thicker layer of oxidation relative to the non-implanted lower portions of the sidewalls.
Public/Granted literature
- US20220359670A1 TECHNIQUE FOR REDUCING GATE INDUCED DRAIN LEAKAGE IN DRAM CELLS Public/Granted day:2022-11-10
Information query
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