Invention Grant
- Patent Title: NPNP layered MOS-gated trench device having lowered operating voltage
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Application No.: US17539063Application Date: 2021-11-30
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Publication No.: US11610987B2Publication Date: 2023-03-21
- Inventor: Paul M Moore , Vladimir Rodov , Richard A Blanchard
- Applicant: Pakal Technologies, LLC
- Applicant Address: US CA San Francisco
- Assignee: Pakal Technologies, LLC
- Current Assignee: Pakal Technologies, LLC
- Current Assignee Address: US CA San Francisco
- Agency: Patent Law Group
- Agent Brian Ogonowsky
- Main IPC: H01L29/745
- IPC: H01L29/745 ; H01L29/423

Abstract:
An npnp layered switch is modified to have a composite anode structure. Instead of the continuous p-type bottom anode layer of a typical npnp IGTO device, thyristor, or IGBT, the composite anode is formed of a segmented p-type layer with gaps containing n-type semiconductor material. The n-type material forms a majority carrier path between the bottom anode electrode and the n-type collector of the vertical npn bipolar transistor. When a trenched gate is biased high, the majority carrier path is created between the bottom anode electrode and the top cathode electrode. Such a current path operates at very low operating voltages, starting at slightly above 0 volts. Above operating voltages of about 1.0 volts, the npnp layered switch operates normally and uses regenerative bipolar transistor action to conduct a vast majority of the current. The two current paths conduct in parallel.
Public/Granted literature
- US20220376095A1 NPNP LAYERED MOS-GATED TRENCH DEVICE HAVING LOWERED OPERATING VOLTAGE Public/Granted day:2022-11-24
Information query
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