Invention Grant
- Patent Title: Method for forming RRAM with a barrier layer
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Application No.: US17171278Application Date: 2021-02-09
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Publication No.: US11611038B2Publication Date: 2023-03-21
- Inventor: Fu-Chen Chang , Kuo-Chi Tu , Wen-Ting Chu , Chu-Jie Huang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: H01L47/00
- IPC: H01L47/00 ; H01L45/00 ; H01L27/24

Abstract:
Various embodiments of the present application are directed towards a resistive random-access memory (RRAM) cell comprising a barrier layer to constrain the movement of metal cations during operation of the RRAM cell. In some embodiments, the RRAM cell further comprises a bottom electrode, a top electrode, a switching layer, and an active metal layer. The switching layer, the barrier layer, and the active metal layer are stacked between the bottom and top electrodes, and the barrier layer is between the switching and active metal layers. The barrier layer is conductive and between has a lattice constant less than that of the active metal layer.
Public/Granted literature
- US20210184114A1 RRAM WITH A BARRIER LAYER Public/Granted day:2021-06-17
Information query
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