Invention Grant
- Patent Title: Method and system for latch-up prevention
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Application No.: US17129195Application Date: 2020-12-21
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Publication No.: US11615227B2Publication Date: 2023-03-28
- Inventor: Po-Chia Lai , Kuo-Ji Chen , Wen-Hao Chen , Wun-Jie Lin , Yu-Ti Su , Rabiul Islam , Shu-Yi Ying , Stefan Rusu , Kuan-Te Li , David Barry Scott
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Merchant & Gould PC
- Main IPC: G06F30/30
- IPC: G06F30/30 ; G06F30/392 ; H01L27/02 ; G01R31/50 ; G06F30/327 ; G06F30/367 ; G06F30/398 ; G06F117/02

Abstract:
An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations.
Public/Granted literature
- US20210117605A1 METHOD AND SYSTEM FOR LATCH-UP PREVENTION Public/Granted day:2021-04-22
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