Invention Grant
- Patent Title: Enhancing hierarchical depth buffer culling efficiency via mask accumulation
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Application No.: US17446260Application Date: 2021-08-27
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Publication No.: US11615585B2Publication Date: 2023-03-28
- Inventor: Saikat Mandal , Vasanth Ranganathan
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Jaffery Watson Mendonsa & Hamilton LLP
- Main IPC: G06T15/40
- IPC: G06T15/40 ; G06T1/20 ; G06T1/60

Abstract:
Embodiments described herein provide for a technique to improve the culling efficiency of coarse depth testing. One embodiment provides for a graphics processor that includes a depth pipeline that is configured to perform a method to track a history of source fragments that are tested against a destination tile. When a combination of partial fragments sum to full coverage, the most conservative source far depth value is used instead of the previous destination far depth value. When the combination sums to partial coverage, the previous destination far depth value is retained.
Public/Granted literature
- US20210390768A1 ENHANCING HIERARCHICAL DEPTH BUFFER CULLING EFFICIENCY VIA MASK ACCUMULATION Public/Granted day:2021-12-16
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