- Patent Title: Reducing spacing between conductive features through implantation
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Application No.: US17150552Application Date: 2021-01-15
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Publication No.: US11615982B2Publication Date: 2023-03-28
- Inventor: Kuo-Ju Chen , Su-Hao Liu , Liang-Yin Chen , Huicheng Chang , Yee-Chia Yeo , Meng-Han Chou
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L29/78 ; H01L23/522

Abstract:
A method includes forming a first dielectric layer over a source/drain region, and forming a source/drain contact plug over and electrically connecting to the source/drain region. A top portion of the source/drain contact plug has a first lateral dimension. An implantation process is performed to implant a dopant into the first dielectric layer. The implantation process results in the source/drain contact plug to have a second lateral dimension smaller than the first lateral dimension. The method further includes forming a second dielectric layer over the etch stop layer, and forming a gate contact plug adjacent to the source/drain contact plug.
Public/Granted literature
- US20220230911A1 Reducing Spacing Between Conductive Features Through Implantation Public/Granted day:2022-07-21
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