Invention Grant
- Patent Title: Backside via with a low-k spacer
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Application No.: US17213889Application Date: 2021-03-26
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Publication No.: US11615987B2Publication Date: 2023-03-28
- Inventor: Po-Yu Huang , I-Wen Wu , Chen-Ming Lee , Fu-Kai Yang , Mei-Yun Wang
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/8234
- IPC: H01L21/8234 ; H01L29/06 ; H01L29/786 ; H01L29/423

Abstract:
A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary method includes forming a fin-shaped structure extending from a front side of a substrate, recessing a source region of the fin-shaped structure to form a source opening, forming a semiconductor plug under the source opening, exposing the semiconductor plug from a back side of the substrate, selectively removing a first portion of the substrate without removing a second portion of the substrate adjacent to the semiconductor plug, forming a backside dielectric layer over a bottom surface of the workpiece, replacing the semiconductor plug with a backside contact, and selectively removing the second portion of the substrate to form a gap between the backside dielectric layer and the backside contact. By forming the gap, a parasitic capacitance between the backside contact and an adjacent gate structure may be advantageously reduced.
Public/Granted literature
- US20220310455A1 BACKSIDE VIA WITH A LOW-K SPACER Public/Granted day:2022-09-29
Information query
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