Invention Grant
- Patent Title: Quantum dot devices with passive barrier elements in a quantum well stack between metal gates
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Application No.: US16143641Application Date: 2018-09-27
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Publication No.: US11616126B2Publication Date: 2023-03-28
- Inventor: Hubert C. George , Ravi Pillarisetty , Lester Lampert , James S. Clarke , Nicole K. Thomas , Roman Caudillo , David J. Michalak , Jeanette M. Roberts
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Akona IP PC
- Main IPC: H01L29/12
- IPC: H01L29/12 ; H01L29/66 ; B82Y10/00 ; G06N10/00 ; H01L29/76 ; H01L29/06 ; H01L29/778 ; H01L29/423 ; H01L29/78 ; H01L29/165 ; H01L29/82 ; H01L21/8234 ; H01L29/16
Abstract:
A quantum dot device is disclosed that includes a quantum well stack, a first and a second plunger gates above the quantum well stack, and a passive barrier element provided in a portion of the quantum well stack between the first and the second plunger gates. The passive barrier element may serve as means for localizing charge in the quantum dot device and may be used to replace charge localization control by means of a barrier gate. In general, a quantum dot device with a plurality of plunger gates provided over a given quantum well stack may include a respective passive barrier element between any, or all, of adjacent plunger gates in the manner as described for the first and second plunger gates.
Public/Granted literature
- US20190043950A1 QUANTUM DOT DEVICES WITH PASSIVE BARRIER ELEMENTS IN A QUANTUM WELL STACK BETWEEN METAL GATES Public/Granted day:2019-02-07
Information query
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