- Patent Title: Physically-tagged data cache memory that uses translation context to reduce likelihood that entries allocated during execution under one translation context are accessible during execution under another translation context
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Application No.: US17005307Application Date: 2020-08-27
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Publication No.: US11620377B2Publication Date: 2023-04-04
- Inventor: John G. Favor , Srivatsan Srinivasan
- Applicant: Ventana Micro Systems Inc.
- Applicant Address: US CA San Jose
- Assignee: Ventana Micro Systems Inc.
- Current Assignee: Ventana Micro Systems Inc.
- Current Assignee Address: US CA San Jose
- Agency: Huffman Law Group, P.C.
- Agent E. Alan Davis
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F21/52 ; G06F21/55 ; G06F12/14 ; G06F12/1045 ; G06F12/0871 ; G06F12/0895 ; G06F9/455 ; G06F12/0811
Abstract:
A physically-tagged data cache memory mitigates side channel attacks by using a translation context (TC). With each entry allocation, control logic uses the received TC to perform the allocation, and with each access uses the received TC in a hit determination. The TC includes an address space identifier (ASID), virtual machine identifier (VMID), a privilege mode (PM) or translation regime (TR), or combination thereof. The TC is included in a tag of the allocated entry. Alternatively, or additionally, the TC is included in the set index to select a set of entries of the cache memory. Also, the TC may be hashed with address index bits to generate a small tag also included in the allocated entry used to generate an access early miss indication and way select.
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