Invention Grant
- Patent Title: Electrical overlay measurement methods and structures for wafer-to-wafer bonding
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Application No.: US17189548Application Date: 2021-03-02
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Publication No.: US11621202B2Publication Date: 2023-04-04
- Inventor: Liang Li , Jenny Qin , Minna Li
- Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
- Applicant Address: US CA San Jose
- Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
- Current Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
- Current Assignee Address: US CA San Jose
- Agency: The Marbury Law Group PLLC
- Main IPC: H01L23/58
- IPC: H01L23/58 ; H01L29/10 ; H01L21/66 ; H01L25/18 ; H01L23/00 ; H01L23/48 ; H01L25/00 ; H01L25/065

Abstract:
Alignment of a first wafer bonded to a second wafer can be determined using electrical wafer alignment methods. A wafer stack can be formed by overlaying a second wafer over a first wafer such that second metal bonding pads of the second wafer contact first metal bonding pads of the first wafer. A leakage current or a capacitance measurement step is performed between first alignment diagnostic structures in the first wafer and second alignment diagnostic structures in the second wafer for multiple mating pairs of first semiconductor dies in the first wafer and second semiconductor dies in the second wafer to determine the alignment.
Public/Granted literature
- US20220285233A1 ELECTRICAL OVERLAY MEASUREMENT METHODS AND STRUCTURES FOR WAFER-TO-WAFER BONDING Public/Granted day:2022-09-08
Information query
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