Invention Grant
- Patent Title: Integrated circuit package and method
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Application No.: US16684913Application Date: 2019-11-15
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Publication No.: US11621244B2Publication Date: 2023-04-04
- Inventor: Chen-Hua Yu , Chuei-Tang Wang , Chieh-Yen Chen , Wei Ling Chang
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L23/00 ; H01L21/48 ; H01L23/48 ; H01L25/00

Abstract:
In an embodiment, a device includes: a first die array including first integrated circuit dies, orientations of the first integrated circuit dies alternating along rows and columns of the first die array; a first dielectric layer surrounding the first integrated circuit dies, surfaces of the first dielectric layer and the first integrated circuit dies being planar; a second die array including second integrated circuit dies on the first dielectric layer and the first integrated circuit dies, orientations of the second integrated circuit dies alternating along rows and columns of the second die array, front sides of the second integrated circuit dies being bonded to front sides of the first integrated circuit dies by metal-to-metal bonds and by dielectric-to-dielectric bonds; and a second dielectric layer surrounding the second integrated circuit dies, surfaces of the second dielectric layer and the second integrated circuit dies being planar.
Public/Granted literature
- US20210151408A1 Integrated Circuit Package and Method Public/Granted day:2021-05-20
Information query
IPC分类: