Invention Grant
- Patent Title: Diffused bitline replacement in stacked wafer memory
-
Application No.: US17107710Application Date: 2020-11-30
-
Publication No.: US11621246B2Publication Date: 2023-04-04
- Inventor: Stephen Morein
- Applicant: ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
- Applicant Address: US CA San Jose
- Assignee: ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
- Current Assignee: ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
- Current Assignee Address: US CA San Jose
- Agency: Knobbe, Martens, Olson & Bear LLP
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L25/065 ; H01L29/08 ; H01L23/528 ; H01L29/45 ; H01L21/8234 ; H01L25/00 ; H01L21/02 ; H01L21/768 ; H01L21/321 ; H01L27/105

Abstract:
Techniques are disclosed herein for creating metal BLs in stacked wafer memory. Using techniques described herein, metal BLs are created on a bottom surface of a wafer. The metal BLs can be created using different processes. In some configurations, a salicide process is utilized. In other configurations, a damascene process is utilized. Using metal reduces the resistance of the BLs as compared to using non-metal diffused BLs. In some configurations, wafers are stacked and bonded together to form three-dimensional memory structures.
Public/Granted literature
- US20210111161A1 DIFFUSED BITLINE REPLACEMENT IN STACKED WAFER MEMORY Public/Granted day:2021-04-15
Information query
IPC分类: