An electronic device may include a first conductive line, a second conductive line, a memory cell and a liner layer. The first conductive line may be extending in a first direction. The second conductive line may be arranged over the first conductive line and extending in a second direction that intersects with the first direction. The memory cell may be arranged between the first conductive line and the second conductive line in regions of intersection between the first conductive line and the second conductive line. The liner layer may be configured to surround the memory cell in the first direction and the second direction. The liner layer may include a potential well.