Invention Grant
- Patent Title: Non-planar integrated circuit structures having asymmetric source and drain trench contact spacing
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Application No.: US16260600Application Date: 2019-01-29
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Publication No.: US11621334B2Publication Date: 2023-04-04
- Inventor: Said Rami , Hyung-Jin Lee , Surej Ravikumar , Kinyip Phoa
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L29/417
- IPC: H01L29/417 ; H01L29/66 ; H01L29/78 ; H01L27/088 ; H01L29/06 ; H01L29/08 ; H01L27/12 ; G06F13/10

Abstract:
Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication. In an example, an integrated circuit structure includes a fin including silicon. A gate structure is over the fin, the gate structure having a center. A conductive source trench contact is over the fin, the conductive source trench contact having a center spaced apart from the center of the gate structure by a first distance. A conductive drain trench contact is over the fin, the conductive drain trench contact having a center spaced apart from the center of the gate structure by a second distance, the second distance greater than the first distance by a factor of three.
Public/Granted literature
- US20200243655A1 NON-PLANAR INTEGRATED CIRCUIT STRUCTURES HAVING ASYMMETRIC SOURCE AND DRAIN TRENCH CONTACT SPACING Public/Granted day:2020-07-30
Information query
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