Invention Grant
- Patent Title: Method of making split-gate non-volatile memory cells with erase gates disposed over word line gates
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Application No.: US17701840Application Date: 2022-03-23
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Publication No.: US11621335B2Publication Date: 2023-04-04
- Inventor: Chunming Wang , Xian Liu , Guo Xiang Song , Leo Xing , Nhan Do
- Applicant: Silicon Storage Technology, Inc.
- Applicant Address: US CA San Jose
- Assignee: Silicon Storage Technology, Inc.
- Current Assignee: Silicon Storage Technology, Inc.
- Current Assignee Address: US CA San Jose
- Agency: DLA Piper LLP (US)
- Priority: CN202011060967.0 20200930
- Main IPC: G11C11/34
- IPC: G11C11/34 ; H01L29/423 ; H01L29/788 ; H01L29/66 ; G11C16/04

Abstract:
A memory device, and method of making the same, that includes a substrate of semiconductor material of a first conductivity type, first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a first channel region in the substrate extending between the first and second regions, a first floating gate disposed over and insulated from a first portion of the first channel region adjacent to the second region, a first coupling gate disposed over and insulated from the first floating gate, a first word line gate disposed over and insulated from a second portion of the first channel region adjacent the first region, and a first erase gate disposed over and insulated from the first word line gate.
Public/Granted literature
- US20220216316A1 METHOD OF MAKING SPLIT-GATE NON-VOLATILE MEMORY CELLS WITH ERASE GATES DISPOSED OVER WORD LINE GATES Public/Granted day:2022-07-07
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