- Patent Title: Nano-wall integrated circuit structure with high integrated density
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Application No.: US17367573Application Date: 2021-07-05
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Publication No.: US11621349B2Publication Date: 2023-04-04
- Inventor: Ping Li , Yongbo Liao , Xianghe Zeng , Yaosen Li , Ke Feng , Chenxi Peng , Zhaoxi Hu , Fan Lin , Xuanlin Xiong , Tao He
- Applicant: University of Electronic Science and Technology of China
- Applicant Address: CN Chengdu
- Assignee: University of Electronic Science and Technology of China
- Current Assignee: University of Electronic Science and Technology of China
- Current Assignee Address: CN Chengdu
- Agency: Central California IP Group, P.C.
- Agent Andrew D. Fortney
- Priority: CN202011244744.X 20201110
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/417 ; H01L29/10
Abstract:
A nano-wall integrated circuit structure with high integration density is disclosed, which relates to the fields of microelectronic technology and integrated circuits (IC). Based on the different device physical principles with MOSFETs in traditional ICs, the nano-wall integrated circuit unit structure (Nano-Wall FET, referred to as NWaFET) with high integration density can improve the integration of the IC, significantly shorten the channel length, improve the flexibility of the device channel width-to-length ratio adjustment, and save chip area.
Public/Granted literature
- US20220149198A1 Nano-wall Integrated Circuit Structure with High Integrated Density Public/Granted day:2022-05-12
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