Invention Grant
- Patent Title: Capacitively-coupled stacked class-d oscillators for galvanic isolation
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Application No.: US17732026Application Date: 2022-04-28
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Publication No.: US11621670B1Publication Date: 2023-04-04
- Inventor: Simone Spataro , Salvatore Coffa , Egidio Ragonese
- Applicant: STMicroelectronics S.r.l. , Università degli studi di Catania
- Applicant Address: IT Agrate Brianza; IT Catania
- Assignee: STMicroelectronics S.r.l.,Università degli studi di Catania
- Current Assignee: STMicroelectronics S.r.l.,Università degli studi di Catania
- Current Assignee Address: IT Agrate Brianza; IT Catania
- Agency: Slater Matsil, LLP
- Main IPC: H03B5/12
- IPC: H03B5/12 ; H03K3/0231 ; H03K3/011

Abstract:
An oscillator circuit includes a total of N (N≥2) class-D oscillator circuits stacked together between a supply voltage node and a reference voltage node. The output ports of adjacent class-D oscillator circuits in the disclosed oscillator circuit are coupled together by capacitors to ensure frequency and phase synchronization for the frequency signals generated by the class-D oscillator circuits. Compared with a reference oscillator circuit formed of a single class-D oscillator circuit, the oscillation amplitude of each of the class-D oscillator circuits in the disclosed oscillator circuit is 1/N of that of the reference oscillator circuit, and the current consumption of the disclosed oscillator circuit is 1/N of that of the reference oscillator circuit.
Information query