Invention Grant
- Patent Title: Low area and high speed termination detection circuit with voltage clamping
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Application No.: US17374319Application Date: 2021-07-13
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Publication No.: US11621711B2Publication Date: 2023-04-04
- Inventor: Anant Shankar Kamath , Kanteti Amar , Bharath Kumar Singareddy , Rakesh Hariharan
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Valerie M. Davis; Frank D. Cimino
- Main IPC: H03K19/00
- IPC: H03K19/00

Abstract:
Methods, apparatus, systems, and articles of manufacture corresponding to a low area and high speed termination detection circuit with voltage clamping are disclosed. An example apparatus includes a transistor including a first control terminal, first current terminal and a second current terminal, the second current terminal adapted to be coupled to a load. The apparatus further includes a logic gate including an input coupled to the first current terminal. The apparatus further includes a current source including a second control terminal, a third current terminal coupled to a voltage rail and a fourth current terminal coupled to the first current terminal and the input of the logic gate.
Public/Granted literature
- US20230022405A1 LOW AREA AND HIGH SPEED TERMINATION DETECTION CIRCUIT WITH VOLTAGE CLAMPING Public/Granted day:2023-01-26
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