Invention Grant
- Patent Title: Systems and methods for semiconductor defect-guided burn-in and system level tests
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Application No.: US17372292Application Date: 2021-07-09
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Publication No.: US11624775B2Publication Date: 2023-04-11
- Inventor: Robert J. Rathert , David W. Price , Chet V. Lenox , Oreste Donzella , John Charles Robinson
- Applicant: KLA Corporation
- Applicant Address: US CA Milpitas
- Assignee: KLA Corporation
- Current Assignee: KLA Corporation
- Current Assignee Address: US CA Milpitas
- Agency: Suiter Swantz pc llo
- Main IPC: G01R31/28
- IPC: G01R31/28 ; H01L21/66

Abstract:
Systems and methods for semiconductor defect-guided burn-in and system level tests (SLT) are configured to receive a plurality of inline defect part average testing (I-PAT) scores from an inline defect part average testing (I-PAT) subsystem, where the plurality of I-PAT scores is generated by the I-PAT subsystem based on semiconductor die data for a plurality of semiconductor dies, where the semiconductor die data includes characterization measurements for the plurality of semiconductor dies, where each I-PAT score of the plurality of I-PAT scores represents a defectivity determined by the I-PAT subsystem based on a characterization measurement of a corresponding semiconductor die of the plurality of semiconductor dies; apply one or more rules to the plurality of I-PAT scores during a dynamic decision-making process; and generate one or more defect-guided dispositions for at least one semiconductor die of the plurality of semiconductor dies based on the dynamic decision-making process.
Public/Granted literature
- US20220390505A1 SYSTEMS AND METHODS FOR SEMICONDUCTOR DEFECT-GUIDED BURN-IN AND SYSTEM LEVEL TESTS Public/Granted day:2022-12-08
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