Invention Grant
- Patent Title: Wear leveling in EEPROM emulator formed of flash memory cells
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Application No.: US17571443Application Date: 2022-01-07
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Publication No.: US11626176B2Publication Date: 2023-04-11
- Inventor: Guangming Lin , Xiaozhou Qian , Xiao Yan Pi , Vipin Tiwari , Zhenlin Ding
- Applicant: Silicon Storage Technology, Inc.
- Applicant Address: US CA San Jose
- Assignee: Silicon Storage Technology, Inc.
- Current Assignee: Silicon Storage Technology, Inc.
- Current Assignee Address: US CA San Jose
- Agency: DLA Piper LLP US
- Priority: CN202010106388.9 20200221
- Main IPC: G11C16/04
- IPC: G11C16/04 ; G11C16/10 ; G11C16/14 ; G11C16/26 ; G11C16/34 ; G06F12/02

Abstract:
The present embodiments relate to systems and methods for implementing wear leveling in a flash memory device that emulates an EEPROM. The embodiments utilize an index array, which stores an index word for each logical address in the emulated EEPROM. The embodiments comprise a system and method for receiving an erase command and a logical address, the logical address corresponding to a sector of physical words of non-volatile memory cells in an array of non-volatile memory cells, the sector comprising a first physical word, a last physical word, and one or more physical words between the first physical word and the last physical word; when a current word, identified by an index bit, is the last physical word in the sector, erasing the sector; and when the current word is not the last physical word in the sector, changing a next index bit.
Public/Granted literature
- US20220130477A1 WEAR LEVELING IN EEPROM EMULATOR FORMED OF FLASH MEMORY CELLS Public/Granted day:2022-04-28
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