Invention Grant
- Patent Title: Semiconductor structure and planarization method thereof
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Application No.: US15438883Application Date: 2017-02-22
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Publication No.: US11626315B2Publication Date: 2023-04-11
- Inventor: Chun-Jung Huang , Hsu-Shui Liu , Han-Wen Liao , Yu-Yao Huang , Hsiao-Wei Chen , Yung-Lin Hsu , Kuang-Huan Hsu
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Birch, Stewart, Kolasch & Birch, LLP
- Main IPC: H01L21/3105
- IPC: H01L21/3105 ; H01L21/762 ; H01L29/06 ; H01L29/66 ; H01L21/02 ; H01L21/768 ; H01L29/78
Abstract:
A planarization method includes forming a dielectric layer over a polish stop layer. The dielectric layer is polished until reaching the polish stop layer, and the polished dielectric layer has a concave top surface. A compensation layer is formed over the concave top surface. The compensation layer is polished.
Public/Granted literature
- US20180151412A1 SEMICONDUCTOR STRUCTURE AND PLANARIZATION METHOD THEREOF Public/Granted day:2018-05-31
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