Invention Grant
- Patent Title: Methods of fabricating semiconductor devices with mixed threshold voltages boundary isolation of multiple gates and structures formed thereby
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Application No.: US17097578Application Date: 2020-11-13
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Publication No.: US11626327B2Publication Date: 2023-04-11
- Inventor: Kuo-Cheng Chiang , Chung-Wei Hsu , Lung-Kun Chu , Jia-Ni Yu , Chih-Hao Wang , Mao-Lin Huang
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Birch, Stewart, Kolasch & Birch, LLP
- Main IPC: H01L21/70
- IPC: H01L21/70 ; H01L21/8238 ; H01L29/06 ; H01L29/66 ; H01L29/49 ; H01L27/092 ; H01L21/308 ; H01L21/033 ; H01L21/28 ; H01L29/78

Abstract:
A semiconductor device is provided. The semiconductor device includes a plurality of first semiconductor nanosheets spaced apart from each other and in a p-type device region, and a plurality of second semiconductor nanosheets spaced apart from each other and in an n-type device region. The semiconductor device includes an isolation structure formed at a boundary between the p-type and n-type device regions, and a first hard mask layer formed over the first semiconductor nanosheets. The semiconductor device also includes a second hard mask layer formed over the second semiconductor nanosheets, and a p-type work function layer surrounding each of the first semiconductor nanosheets and the first hard mask layer.
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