A semiconductor device can include a pad layer including at least one pad structure having a core area surrounded by a peripheral area, and a transistor over the core area. The transistor includes a channel structure extending vertically and a gate structure all around a sidewall portion of the channel structure. The channel structure has a source region and a drain region on opposing ends of a vertical channel region. The channel structure is configured to be electrically coupled to the pad structure. The semiconductor device can further include a first vertical interconnect structure that contacts a top surface of the channel structure, a second vertical interconnect structure that contacts the peripheral area and is configured to be coupled to a bottom surface of the channel structure via the pad structure, and a third vertical interconnect structure that is positioned away from the channel structure and contacts the gate structure.