Invention Grant
- Patent Title: Package comprising a solder resist layer configured as a seating plane for a device
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Application No.: US16590299Application Date: 2019-10-01
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Publication No.: US11626336B2Publication Date: 2023-04-11
- Inventor: Daniel Garcia , Kinfegebriel Amera Mengistie , Francesco Carrara , Chang-Ho Lee , Ashish Alawani , Mark Kuhlman , John Jong-Hoon Lee , Jeongkeun Kim , Xiaoju Yu , Supatta Niramarnkarn
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Qualcomm Incorporated
- Main IPC: H01L23/16
- IPC: H01L23/16 ; H01L21/48 ; H01L21/56 ; H01L23/31 ; H01L23/498 ; H01L23/552 ; H01L23/00
Abstract:
A package that includes a substrate having a first surface; a solder resist layer coupled to the first surface of the substrate; a device located over the solder resist layer such that a portion of the device touches the solder resist layer; and an encapsulation layer located over the solder resist layer such that the encapsulation layer encapsulates the device. The solder resist layer is configured as a seating plane for the device. The device is located over the solder resist layer such that a surface of the device facing the substrate is approximately parallel to the first surface of the substrate. The solder resist layer includes at least one notch. The device is located over the solder resist layer such that at least one corner of the device touches the at least one notch.
Public/Granted literature
- US20210098320A1 PACKAGE COMPRISING A SOLDER RESIST LAYER CONFIGURED AS A SEATING PLANE FOR A DEVICE Public/Granted day:2021-04-01
Information query
IPC分类:
