Invention Grant
- Patent Title: Method of manufacturing FinFETs having barrier layers with specified SiGe doping concentration
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Application No.: US16370722Application Date: 2019-03-29
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Publication No.: US11626507B2Publication Date: 2023-04-11
- Inventor: Martin Christopher Holland , Marcus Johannes Henricus Van Dal
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: McDermott Will & Emery LLP
- Main IPC: H01L29/08
- IPC: H01L29/08 ; H01L29/165 ; H01L29/167 ; H01L29/78 ; H01L21/311 ; H01L21/306 ; H01L29/66 ; H01L29/06 ; H01L21/02 ; H01L29/36 ; H01L29/423

Abstract:
In a method of manufacturing a semiconductor device, a gate structure is formed over a fin structure. A source/drain region of the fin structure is recessed. A first semiconductor layer is formed over the recessed source/drain region. A second semiconductor layer is formed over the first semiconductor layer. The fin structure is made of SixGe1-x, where 0≤x≤0.3, the first semiconductor layer is made of SiyGe1-y, where 0.45≤y≤1.0, and the second semiconductor layer is made of SizGe1-z, where 0≤z≤0.3.
Public/Granted literature
- US11581424B2 Method of manufacturing FinFETs having barrier layers with specified SiGe doping concentration Public/Granted day:2023-02-14
Information query
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